Đọc datasheet

/* Reference manual muc 11.3.1 "ADC on-off control" ghi ro:

     1. Set ADON bit -> ADC ra khoi che do ngu
     2. CHO t_STAB truoc khi bat dau chuyen doi
     3. Set ADON lan NUA hoac set SWSTART -> bat dau chuyen doi

   Va bang dac tinh trong DATASHEET cho biet t_STAB = 3 micro giay.

   Bo qua buoc 2 thi lan doc dau tien cho gia tri sai. */

ADC1->CR2 |= (1u << 0);      /* buoc 1: ADON */

tre_us(3u);                  /* buoc 2: cho on dinh */

ADC1->CR2 |= (1u << 30);     /* buoc 3: SWSTART */

8.4.1  GPIO port mode register (GPIOx_MODER)

Address offset: 0x00
Reset value:    0xA800 0000 for port A
                0x0000 0280 for port B
                0x0000 0000 for other ports

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+-----+-----+-----+-----+-----+-----+-----+-----+
|MODER15 |MODER14 |MODER13 |MODER12 |MODER11 |...
+-----+-----+-----+-----+-----+-----+-----+-----+
| rw rw | rw rw | rw rw | rw rw | rw rw | ...

Bits 2y:2y+1  MODERy[1:0]: Port x configuration bits (y = 0..15)
              These bits are written by software to configure
              the I/O direction mode.
                00: Input (reset state)
                01: General purpose output mode
                10: Alternate function mode
                11: Analog mode

Table 9. Alternate function mapping

Port | AF0  | AF1   | AF2   | AF4    | AF5   | AF6   | AF7      | AF9
-----+------+-------+-------+--------+-------+-------+----------+------
PA0  | -    | TIM2  | TIM5  | -      | -     | -     | USART2   | -
     |      | _CH1  | _CH1  |        |       |       | _CTS     |
PA2  | -    | TIM2  | TIM5  | -      | -     | -     | USART2   | -
     |      | _CH3  | _CH3  |        |       |       | _TX      |
PA5  | -    | TIM2  | -     | -      | SPI1  | -     | -        | -
     |      | _CH1  |       |        | _SCK  |       |          |
PA6  | -    | TIM1  | TIM3  | -      | SPI1  | -     | -        | -
     |      | _BKIN | _CH1  |        | _MISO |       |          |
PA9  | -    | TIM1  | -     | I2C3   | -     | -     | USART1   | -
     |      | _CH2  |       | _SMBA  |       |       | _TX      |
PA10 | -    | TIM1  | -     | -      | -     | -     | USART1   | -
     |      | _CH3  |       |        |       |       | _RX      |

/* Muon dung PA6 lam PWM tu TIM3 kenh 1.
   Tra bang: dong PA6, cot AF2 -> TIM3_CH1. Vay can AF2. */

/* AFR[0] lo chan 0 toi 7, AFR[1] lo chan 8 toi 15.
   Moi chan bon bit. */
static inline void gpio_dat_af(GPIO_TypeDef *cong, uint8_t chan, uint8_t af)
{
    uint8_t  chi_so = (uint8_t)(chan >> 3);          /* 0 hoac 1 */
    uint8_t  vi_tri = (uint8_t)((chan & 7u) * 4u);   /* 0, 4, 8, ... 28 */
    uint32_t r      = cong->AFR[chi_so];

    r &= ~(0xFu << vi_tri);
    r |=  ((uint32_t)(af & 0xFu) << vi_tri);

    cong->AFR[chi_so] = r;
}

void pwm_chan_khoi_tao(void)
{
    RCC->AHB1ENR |= (1u << 0);

    gpio_dat_af(GPIOA, 6u, 2u);                      /* AF2 = TIM3_CH1 */

    GPIOA->MODER &= ~(3u << (6 * 2));
    GPIOA->MODER |=  (2u << (6 * 2));                /* 10 = che do thay the */
}

2.1.6  Delay after an RCC peripheral clock enabling

Description
  A delay between an RCC peripheral clock enable and the effective
  peripheral enabling should be taken into account in order to manage
  the peripheral read/write to registers.

  This delay depends on the peripheral mapping:
    - If the peripheral is mapped on AHB: the delay is 2 AHB cycles
    - If the peripheral is mapped on APB: the delay is 2 APB cycles

Workaround
  Use a dummy read of the peripheral register after enabling
  its clock, or add a delay of 2 cycles.

/* Cấu hình ADC1 kênh 0.
   RM0368 muc 11.3.1: sau khi set ADON phai cho t_STAB.
   DS9716 bang 67: t_STAB = 3 us cho STM32F401.
   ES0255 muc 2.4.2: khong dung ADC cung DMA o che do quet
                     tren revision A.                        */
void adc_khoi_tao(void)
{
    ...
}

/* Ba dong chu thich nay tiet kiem cho nguoi doc sau, ke ca chinh ban,
   khoang mot gio tra cuu. Chung cung la thu duy nhat noi cho nguoi
   bao tri biet vi sao co dong tre_us(3) tuong nhu vo nghia kia. */